A(16:0)
tAVAV
DQ(31:0)
Previous Valid Data
Assumptions:
1. E1 and G < VIL (max) and E2 and W > VIH (min)
tAXQX
Valid Data
tAVQV
Figure 3a. SRAM Read Cycle 1: Address Access
A(16:0)
Latter of E1 low
and E2 high
DQ(31:0)
tETQV
tETQX
tEFQZ
DATA VALID
Assumptions:
1. G, HHWE, LHWE < VIL (max) and W > VIH (min)
Figure 3b. SRAM Read Cycle 2: Chip Enable Access
A(16:0)
G
tAVQV
tBLQV
tBLQX
tBHQZ
LHWE/HHWE
DQ(31:0)
tGLQX
Assumptions:
1. E1 < VIL (max) , E2 and W > VIH (min)
tGLQV
DATA VALID
tGHQZ
Figure 3c. SRAM Read Cycle 3: Output Enable Access
7