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STA001

RF FRONT-END FOR DIGITAL RADIO

STMicroelectronics 

STA001

ELECTRICAL CHARACTERISTCS (continued)

Symbol

Parameter

Test Condition

Min. Typ. Max. Unit

CRYSTAL OSCILLATOR (T = 25°, VDD-VSS = 3V)

VDC XTAL1, XTAL2 common XOSEL high

mode DC voltage

VDD-

1.1

VDD-

V

0.68

PLLs, SYNTHESIZERS (T = 25°, VDD-VSS = 3V)

ts RF pll loop settling time within 1 KHz final freq. Offset, by using the

1

ms

loop filter of Application board

Pn Total phase noise

contribution

100Hz < ∆f < 1.84Mhz,

Qrf_tank≥20, Qif_tank≥20

1.6

degrms

fREF1 RF pll comparation

frequency

3.68

MHz

fREF2 IF pll comparation

frequency

113.23

KHz

PSP Spurious power level*** RF pll, ∆fc=n*460KHz n=1,2..

IF pll, ∆fc=113.23KHz

-50

dBc

-100

-45 dBc

Nprog1 RF PLL selectable

division ratios

from REF1 to LO1, range covered by a 0.5

step, using a 14.72MHz quartz

1443

(first

used

1454.5)

1506.5

(last

used

1495)

Nprog2 RF PLL selectable

division ratios

from REF1 to LO1, range covered by a 0.5

step, using a 14.725MHz quartz

1443

(first

used

1454)

1506.5

(last

used

1494.5)

Nfix IF PLL fixed division ratios from REF2 to LO2, 1 fixed +2 testing values 987 1034 1081

NREF1 REF1 division ratio

from Crystal oscillator to REF1

4

NREF2 REF2 division ratio

from Crystal oscillator to REF2

130

*** Using loop filter as suggested in application board schematics

RF VCO (T = 25°, VDD-VSS = 3V)

fLO1_1 LO Freq. range

Using 14.72Mhz quartz

fLO1_2 LO Freq. range

Using 14.725Mhz quartz

VFLT1 Freq. control voltage

range

Pin FLT1

VDC TK1, NTK1 DC voltage ENRFOSC high

Zi Input impedance R || C Balanced, TK1, NTK1 pins

1338.14

1375.4 MHz

1338.134375 to 1375.407031 MHz

VSS +

0.2

VDD -

V

0.2

VDD- VDD- VDD-

V

1.3

1.1 0.65

300

Ω

0.2

pF

7/20

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