MU9C4480A-12DC Просмотр технического описания (PDF) - Music Semiconductors

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MU9C4480A-12DC

LANCAMs®

Music Semiconductors 

MU9C4480A/L

PIN DESCRIPTIONS Continued

TEST1, TEST2 (Test, Input, TTL)

These pins enable MUSIC production test modes that are

not usable in an application. They should be connected to

ground, either directly or through a pull-down resistor, or

they may be left unconnected. These pins may not be

implemented on all versions of these products.

VCC, GND (Positive Power Supply, Ground)

These pins are the power supply connections to the

LANCAM. VCC must meet the voltage supply requirements

in the Operating Conditions section relative to the GND

pins, which are at 0 Volts (system reference potential), for

correct operation of the device. All the ground and power

pins must be connected to their respective planes with

adequate bulk and high frequency bypassing capacitors in

close proximity to the device.

FUNCTIONAL DESCRIPTION

The LANCAM is a content-addressable memory (CAM)

with 16-bit I/O for network address filtering and translation,

virtual memory, data compression, caching, and table lookup

applications. The memory consists of static CAM,

organized in 64-bit data fields. Each data field can be

partitioned into a CAM and a RAM subfield on 16-bit

boundaries. The contents of the memory can be randomly

accessed or associatively accessed by the use of a compare.

During automatic comparison cycles, data in the

Comparand register is automatically compared with the

“Valid” entries in the memory array. The Device ID can be

read using a TCO PS instruction (see Table 12 on page 21).

The data inputs and outputs of the LANCAM are

multiplexed for data and instructions over a 16-bit

I/O bus. Internally, data is handled on a 64-bit basis, since

the Comparand register, the mask registers, and each

memory entry are 64 bits wide. Memory entries are globally

configurable into CAM and RAM segments on 16-bit

boundaries, as described in US Patent 5,383,146 assigned

to MUSIC Semiconductors. Seven different CAM/RAM

splits are possible, with the CAM width going from one to

four segments, and the remaining RAM width going from

three to zero segments. Finer resolution on compare width

is possible by invoking a mask register during a compare,

which does global masking on a bit basis. The CAM subfield

contains the associative data, which enters into compares,

while the RAM subfield contains the associated data, which

is not compared. In LAN bridges, the RAM subfield could

hold, for example, port-address and aging information

related to the destination or source address information

held in the CAM subfield of a given location. In a translation

application, the CAM field could hold the dictionary entries,

while the RAM field holds the translations, with almost

instantaneous response.

Each entry has two validity bits (known as Skip bit and Empty

bit) associated with it to define its particular type: empty, valid,

skip, or RAM. When data is written to the active Comparand

register, and the active Segment Control register reaches its

terminal count, the contents of the Comparand register are

automatically compared with the CAM portion of all the valid

entries in the memory array. For added versatility, the

Comparand register can be barrel-shifted right or left one bit at

a time. A Compare instruction can then be used to force

another compare between the Comparand register and the

CAM portion of memory entries of any one of the four validity

types. After a Read or Move from Memory operation, the

validity bits of the location read or moved will be copied into

the Status register, where they can be read from the Status

register using Command Read cycles.

Data can be moved from one of the data registers (CR, MR1, or

MR2) to a memory location that is based on the results of the

last comparison (Highest-Priority Match or Next Free), or to

an absolute address, or to the location pointed to by the active

Address register. Data can also be written directly to the

memory from the DQ bus using any of the above addressing

modes. The Address register may be directly loaded and may

be set to increment or decrement, allowing DMA-type reading

or writing from memory.

Two sets of configuration registers (Control, Segment

Control, Address, Mask Register 1, and Persistent Source

and Destination) are provided to permit rapid context

switching between foreground and background activities.

Writes, reads, moves, and compares are controlled by the

currently active set of configuration registers. The

foreground set would typically be pre-loaded with values

useful for comparing input data, often called filtering, while

the background set would be pre-loaded with values useful

for housekeeping activities such as purging old entries.

Moving from the foreground task of filtering to the

background task of purging can be done by issuing a single

instruction to change the current set of configuration

registers. The match condition of the device is reset

whenever the active register set is changed.

Rev. 3a

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