MU9C5480A-12DI Просмотр технического описания (PDF) - Music Semiconductors

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MU9C5480A-12DI

LANCAMs®

Music Semiconductors 

MU9C4480A/L

GENERAL DESCRIPTION

The MU9C4480A and MU9C4480L LANCAMs are 4096

x 64-bit content-addressable memories (CAMs), with 16-bit

wide interfaces. They are pin compatible with all devices in

the MUSIC LANCAM family.

Content-addressable memories, also known as associative

memories, operate in the converse way to random access

memories (RAM). In RAM, the input to the device is an

address and the output is the data stored at that address.

In CAM, the input is a data sample and the output is a flag

to indicate a match and the address of the matching data.

As a result, CAM searches large databases for matching

data in a short, constant time period, no matter how many

entries are in the database. The ability to search data words

up to 64 bits wide allows large address spaces to be searched

rapidly and efficiently. A patented architecture links each

CAM entry to associated data and makes this data available

for use after a successful compare operation.

The MUSIC LANCAMs are ideal for address filtering and

translation applications in LAN switches and routers. The

LANCAMs are also well suited to encryption, database

accelerators, and image processing.

OPERATIONAL OVERVIEW

To use the LANCAM, the user loads the data into the

Comparand register, which is automatically compared to all

valid CAM locations. The device then indicates whether or

not one or more of the valid CAM locations contains data

that matches the target data. The status of each CAM

location is determined by two validity bits at each memory

location. The two bits are encoded to render four validity

conditions: Valid, Skip, Empty, and Random Access, as

shown in Table 1. The memory can be partitioned into CAM

and associated RAM segments on 16-bit boundaries, but

by using either of the two available mask registers, the

CAM/RAM partitioning can be set at any arbitrary size

between zero and 64 bits.

The LANCAM’s internal data path is 64 bits wide for rapid

internal comparison and data movement. Vertical cascading

of additional LANCAMs in a daisy chain fashion extends

the CAM memory depth for large databases. Cascading

requires no external logic. Loading data to the Control,

Comparand, and mask registers automatically triggers a

compare. Compares may also be initiated by a command to

the device. Associated RAM data is available immediately

after a successful compare operation. The Status register

reports the results of compares including all flags and

addresses. Two mask registers are available and can be used

in two different ways: to mask comparisons or to mask data

writes. The random access validity type allows additional

masks to be stored in the CAM array where they may be

retrieved rapidly.

The device is controlled by a simple four-wire control interface

and commands loaded into the Instruction Decoder. A

powerful instruction set increases the control flexibility and

minimizes software overhead. Additionally, dedicated pins for

match and multiple-match flags enhance performance when

the device is controlled by a state machine. These and other

features make the LANCAM a powerful associative memory

that drastically reduces search delays.

Skip Bit

0

0

1

1

Empty Bit

0

1

0

1

Entry Type

Valid

Empty

Skip

RAM

Table 1: Entry Types vs. Validity Bits

/W

LOW

LOW

HIGH

HIGH

/CM

Cycle Type

LOW

Command Write Cycle

HIGH

Data Write Cycle

LOW

Command Read Cycle

HIGH

Data Read Cycle

Table 2: I/O Cycles

G ND 7

DQ4 8

DQ5 9

V CC 10

V CC 11

TEST 2 12

G ND 13

G ND 14

D Q 6 15

D Q 7 16

V CC 17

4444--ppiinn PPLLCCCC

((TToopp VViieeww))

39 /M A

38 /MI

37 /MF

36 G ND

35 /R ESET

34 V CC

33 V CC

32 TE S T1

31 /E

30 /W

29 G ND

PINOUT DIAGRAM

Rev. 3a

2

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