MU9C4480A-12DC Просмотр технического описания (PDF) - Music Semiconductors

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MU9C4480A-12DC

LANCAMs®

Music Semiconductors 

MU9C4480A/L

OPERATIONAL CHARACTERISTICS Continued

be used for the next memory access referencing the

Address register. A reset sets the Address register to

zero.

Control Register bits CT3 and CT2 set the Address register to

automatically increment or decrement (or not change) during

sequences of Command or Data cycles. The Address register

will change after executing an instruction that includes

M@[AR] or M@aaaH, or after a data access to the end limit

segment (as set in the Segment Control register) when the

persistent source or destination is M@[AR] or M@aaaH.

Either the Foreground or Background Address register will

be active, depending on which register set has been

selected, and only the active Address register will be written

to or read from.

Next Free Address Register (NF)

The LANCAM automatically stores the address of the first

empty memory location in the Next Free Address register,

which is then used as a memory address pointer for M@NF

operations. The Next Free Address register, shown in Table

10 on page 21, can be read using a TCO NF instruction. By

taking /EC LOW during the TCO NF instruction cycle, only

the device with /FI LOW and /FF HIGH will output the

contents of its Next Free Address register, which gives the

Next Free address in a system of daisy-chained devices. The

Next Free address may be read from a specific device in the

chain by setting the Device Select register to the value of the

desired device’s Page address and leaving /EC HIGH.

The Full Flag daisy chain causes only the device whose /FI

input is LOW and /FF output HIGH to respond to an

instruction using the Next Free address. After a reset, the

Next Free Address register is set to zero.

Status Register

The 32-bit Status register, shown in Table 11 on page 21, is the

default source for Command Read cycles. Bit 31 is the internal

Full flag, which will go LOW if the particular device has no

empty memory locations. Bit 30 is the internal Multiple Match

flag, which will go LOW if a Multiple match was detected. Bits

29 and 28 are the Skip and Empty Validity bits, which reflect

the validity of the last memory location read. After a reset, the

Skip and Empty bits will read 11 until a read or move from

memory has occurred. The rest of the Status register down to

bit 1 contains the Page address of the device and the address

of the Highest-priority match as shown in Table 11 on page 21.

After a reset or a no-match condition, the match address bits

will be all 1s. Bit 0 is the internal Match flag, which will go

LOW if a match was found in this particular device.

Comparand Register (CR)

The 64-bit Comparand register is the default destination

for data writes and reads, using the Segment Control register

to select which 16-bit segment of the Comparand register is

to be loaded or read out. The persistent source and

destination for data writes and reads can be changed to the

mask registers or memory by SPS and SPD instructions.

During an automatic or forced compare, the Comparand

register is simultaneously compared against the CAM

portion of all memory locations with the correct validity

condition. Automatic compares always compare against

valid memory locations, while forced compares, using

CMP instructions, can compare against memory locations

tagged with any specific validity condition.

The Comparand register may be shifted one bit at a time to

the right or left by issuing a Shift Right or Shift Left

instruction, with the right and left limits for the wrap-around

determined by the CAM/RAM partitioning set in the Control

register. During shift rights, bits shifted off the LSB of the

CAM partition will reappear at the MSB of the CAM

partition. Likewise, bits shifted off the MSB of the CAM

partition will reappear at the LSB during shift lefts.

Mask Registers (MR1, MR2)

The Mask registers can be used in two different ways, either

to mask compares or to mask data writes and moves. Either

mask register can be selected in the Control register to

mask every compare, or selected by instructions to

participate in data writes or moves to and from Memory. If

a bit in the selected mask register is set to a 0, the

corresponding bit in the Comparand register will enter into

a masked compare operation. If a Mask bit is a 1, the

corresponding bit in the Comparand register will not enter

into a masked compare operation. Bits set to 0 in the mask

register cause corresponding bits in the destination register

or memory location to be updated when masking data writes

or moves, while a bit set to 1 will prevent that bit in the

destination from being changed.

Either the Foreground or Background MR1 can be set active,

but after a reset, the Foreground MR1 is active by default.

MR2 incorporates a sliding mask, where the data can be

replicated one bit at a time to the right or left with no wrap-

around by issuing a Shift Right or Shift Left instruction.

The right and left limits are determined by the CAM/RAM

partitioning set in the Control register. For a Shift Right the

upper limit bit is replicated to the next lower bit, while for a

Shift Left the lower limit bit is replicated to the next higher bit.

Rev. 3a

10

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