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ACS374K

Radiation Hardened Octal D Flip-Flop, Three-State

Intersil 

ACS374MS

April 1995

Radiation Hardened

Octal D Flip-Flop, Three-State

Features

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose 300K RAD (Si)

• Single Event Upset (SEU) Immunity

<1 x 10-10 Errors/Bit-Day (Typ)

• SEU LET Threshold >80 MEV-cm2/mg

• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range: -55oC to +125oC

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range: 4.5V to 5.5V

• Input Logic Levels

- VIL = 30% of VCC Max

- VIH = 70% of VCC Min

• Input Current ≤1µA at VOL, VOH

Description

The Intersil ACS374MS is a radiation hardened octal D-type flip-

flop with three-state outputs. The eight edge-triggered flip-flops

enter data into their registers on the low to high transition of clock

(CP). The Output Enable (OEN) controls the three-state outputs

and is independent of the register operation. When the OEN is

high, the outputs will be in the high impedance state.

The ACS374MS utilizes advanced CMOS/SOS technology to

achieve high-speed operation. This device is a member of the

radiation hardened, high-speed, CMOS/SOS Logic Family.

Pinouts

20 LEAD CERAMIC DUAL-IN-LINE

MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD FINISH C

TOP VIEW

OE 1

Q0 2

D0 3

D1 4

Q1 5

Q2 6

D2 7

D3 8

Q3 9

GND 10

20 VCC

19 Q7

18 D7

17 D6

16 Q6

15 Q5

14 D5

13 D4

12 Q4

11 CP

20 LEAD CERAMIC FLATPACK

MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C

TOP VIEW

OE

Q0

D0

D1

Q1

Q2

D2

D3

Q3

GND

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

VCC

Q7

D7

D6

Q6

Q5

D5

D4

Q4

CP

Ordering Information

PART NUMBER

ACS374DMSR

ACS374KMSR

ACS374D/Sample

ACS374K/Sample

ACS374HMSR

TEMPERATURE RANGE

-55oC to +125oC

-55oC to +125oC

+25oC

+25oC

+25oC

SCREENING LEVEL

Intersil Class S Equivalent

Intersil Class S Equivalent

Sample

Sample

Die

PACKAGE

20 Lead SBDIP

20 Lead Ceramic Flatpack

20 Lead SBDIP

20 Lead Ceramic Flatpack

Die

Truth Table

INPUTS

OUTPUTS

OE

L

L

L

H

H = High Level

L = Low Level

Q0

X = Immaterial

Z = High Impedance

CP

Dn

Qn

H

H

L

L

X

X

Q0

X

X

Z

= Transition from Low to High Level

= the level of Q before the indicated input conditions

were established

Functional Diagram

1 OF 8

FF

D

DQ

CP

COMMON CONTROLS

CP

OE

Q

OE

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

1

Spec Number 518820

File Number 3997

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