5962R9675501TJC Просмотр технического описания (PDF) - Intersil
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5962R9675501TJC Datasheet PDF : 6 Pages
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Die Characteristics
DIE DIMENSIONS:
(2718µm x 4547µm x 483µm ±25.4µm)
107 x 179 x 19mils ±1mil
METALLIZATION:
Type: Al Si Cu
Thickness: 16.0kÅ ±2kÅ
SUBSTRATE POTENTIAL:
Tie substrate to reference ground
BACKSIDE FINISH:
Silicon
Metallization Mask Layout
HS-565ARH-T
PASSIVATION:
Type: Silox (SiO2)
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm2
TRANSISTOR COUNT:
200
PROCESS:
Bipolar, Dielectric Isolation
HS-565ARH-T
VCC
3
(MSB)
BIT 1
BIT 2
VREF OUT
VREF
GND
VREF IN
-VEE
BIPOLAR
RIN
IDAC
OUT
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
10V
SPAN
20V
SPAN
POWER
GND
BIT 12
(LSB)
BIT 10
BIT 11
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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