CD4046BMS Просмотр технического описания (PDF) - Intersil

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CD4046BMS

CMOS Micropower Phase Locked Loop

Intersil 

CD4046BMS

I

II

III

SIGNAL INPUT (TERM 14)

VCO OUTPUT (TERM 4) =

COMPARATOR INPUT (TERM 3)

PHASE COMPARATOR II

OUTPUT (TERM 13)

VCO INPUT (TERM 9) =

∆ LOW-PASS FILTER

OUTPUT

PHASE PULSE (TERM 1)

NOTE: DASHED LINE IS AN OPEN

CIRCUIT CONDITION

(3RD STATE)

-VDD

-VSS

-VDD

-VSS

-VDD

-VSS

FIGURE 15. TYPICAL WAVEFORMS FOR COS/MOS PHASE-LOCKED LOOP

EMPLOYING PHASE COMPARATOR II IN LOCKED CONDICTION

VDD

PHASE 13

COMPARATOR II

OUTPUT

20KΩ

2KΩ

2KΩ

VSS

FIGURE 16. PHASE COMPARATOR II

OUTPUT LOADING CIRCUIT

Chip Dimensions and Pad Layout

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions

as indicated. Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches

7-896

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