HS-80C86RH Просмотр технического описания (PDF) - Intersil

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HS-80C86RH

Radiation Hardened 16-Bit CMOS Microprocessor

Intersil 

Waveforms

CLK (HS-82C85RH OUTPUT)

AD15-AD0

WRITE CYCLE

(NOTE 41)

(RD, INTA,

DT/R = VOH)

DEN

WR

AD15-AD0

INTA CYCLE

(NOTES 41, 43)

(RD, WR = VOH

BHE = VOL)

DT/R

INTA

DEN

HS-80C86RH

T1

T2

TCH1CH2

TCLAV

TCVCTV

AD15-AD0

TCLDV

TCLAX

T3

T4

TCL2CL1

TW

TCLDX2

DATA OUT

TCVCTX

TWHDX

TCVCTV

TWLWH

TCLAZ

TCHCTV

TDVCL

POINTER

TCVCTX

TCLDX1

TCHCTV

TCVCTV

TCVCTV

TCVCTX

SOFTWARE

HALT -

DEN, RD,

WR, INTA = VOH

AD15-AD0

DT/R = INDETERMINATE

TCLAV

INVALID ADDRESS

SOFTWARE HALT

NOTES:

FIGURE 1. BUS TIMING - MINIMUM MODE SYSTEM

41. All signals switch between VOH and VOL unless otherwise specified.

42. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

43. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control signals are shown for

the second INTA cycle.

44. Signals at HS-82C85RH are shown for reference only.

45. All timing measurements are made at 1.5V unless otherwise noted.

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