HEF4071BN Просмотр технического описания (PDF) - Philips Electronics
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HEF4071BN Datasheet PDF : 3 Pages
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Philips Semiconductors
Quadruple 2-input OR gate
Product specification
HEF4071B
gates
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
TYP.
MAX.
TYPICAL EXTRAPOLATION
FORMULA
Propagation delays
In → On
HIGH to LOW
LOW to HIGH
Output transition times
HIGH to LOW
LOW to HIGH
5
10 tPHL
15
5
10
tPLH
15
5
10 tTHL
15
5
10
tTLH
15
55
115 ns
28 ns + (0,55 ns/pF) CL
25
50 ns
15 ns + (0,23 ns/pF) CL
20
35 ns
12 ns + (0,16 ns/pF) CL
45
90 ns
18 ns + (0,55 ns/pF) CL
20
45 ns
9 ns + (0,23 ns/pF) CL
15
30 ns
7 ns + (0,16 ns/pF) CL
60
120 ns
10 ns + (1,0 ns/pF) CL
30
60 ns
9 ns + (0,42 ns/pF) CL
20
40 ns
6 ns + (0,28 ns/pF) CL
60
120 ns
10 ns + (1,0 ns/pF) CL
30
60 ns
9 ns + (0,42 ns/pF) CL
20
40 ns
6 ns + (0,28 ns/pF) CL
Dynamic power
dissipation per
package (P)
VDD
V
TYPICAL FORMULA FOR P (µW)
5
1150 fi + ∑ (foCL) × VDD2
where
10
4800 fi + ∑ (foCL) × VDD2
fi = input freq. (MHz)
15
19 700 fi + ∑ (foCL) × VDD2
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
3
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