ICS672-01 Просмотр технического описания (PDF) - Integrated Circuit Systems
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ICS672-01 Datasheet PDF : 5 Pages
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ICS672-01/02
QuadraClock™ Quadrature Delay Buffer
Operation and Applications
The ICS672-01/02 each provide a total of five output clocks with multiple phase shifts relative to the input
clock (ICLK). Phase shifts of 0° (CLK0), 90° (CLK90), 180° (CLK180), and 270° (CLK270) are provided,
plus one feedback clock (FBCLK). All output clocks will be a multiple of the input clock, as determined by
the table on page 2. Refer to the illustrations in Figure 1 and Figure 2.
FBCLK is connected to the feedback input (FBIN) to provide a zero delay through the ICS672-01/02.
FBCLK has a 0° phase shift from ICLK.
ICLK
CLK0,
FBCLK
CLK90
CLK180
CLK270
Figure 1. Phase alignment of input and output clocks. (x1 multiplier)
ICLK
CLK0,
FBCLK
CLK90
CLK180
CLK270
Figure 2. Phase alignment of input and output clocks. (x2 multiplier)
MDS 672-01/02 C
3
Revision 112200
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