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TZA1000

QIC read-write amplifier

Philips Electronics 

Philips Semiconductors

QIC read-write amplifier

Preliminary specification

TZA1000

FUNCTIONAL DESCRIPTION

The preamplifier

The gain and dynamic range of the symmetrical low noise

preamplifier can be varied to accommodate a wide

variation in input signal amplitude (see Table 11).

The 40 dB and 34 dB gain settings are provided for normal

use. The 40 dB setting offers the lowest noise figure. The

4 dB gain setting is intended for IC testing only.

The servo preamplifier

This low noise preamplifier can be used for reading

signals, such as QIC 3095 (Travan 4) servo signals, via

the recording head write coil. Servo mode is selected

either by resetting bits AI0 and AI1 in the control register

(see Table 9) or by means of the HOLD pin (the HSM

control bit must be set when HOLD goes LOW; see

Table 7). When servo mode is selected, the maximum

total gain is set automatically regardless of, and without

overwriting, gain settings. Fast switch-over from read

mode to servo mode can thus be achieved without having

to alter register values.

Variable gain stage and AGC

The input to the variable gain stage can be switched to the

preamplifier output, to the output of the bias/FB (Feed

Back) circuit, or to the servo preamplifier output. When

using magnetic feedback, the bias/FB circuit output should

be selected (see Table 9).

The AGC range is 15 dB. The gain is programmable in

1 dB steps (see Table 12). If the output signal is too small,

a digital control circuit will increase the gain from minimum

to maximum in approximately 10 ms. If the output signal is

too large, the gain will be reduced from maximum to

minimum in approximately 0.2 ms. These values assume

a 24 MHz clock frequency. The upper limit of the gain

control range can be extended by 6 dB by setting the

G6DB bit in the control register via the serial interface (see

Table 13).

The AGC is frozen while the HOLD input is LOW, the

TZA1000 is writing, or the IC is in servo mode.

The AGC can be operated internally, running on the CLK

clock signal on pin 15 (HOLD HIGH and GFXD LOW; see

Table 12), or externally by means of a software algorithm

(GFXD HIGH). When operated externally, either the DN bit

in the status read register (see Table 17) or the level

measurement in the digital equalizer IC (SZA1000) can be

used as input to the algorithm.

The AGC will maintain outputs OUTA and OUTB at

1.1 V (p-p). Additional level adjustment points are

provided by the 34 or 40 dB preamplifier gain switch (see

Table 11) and the −10 or −4 dB bias output attenuation

switch (see Table 9).

High-pass filter

The HPF (High-Pass Filter) is used to differentiate

yoke-type head signals. It is followed by an additional gain

stage (21 dB). The HPF cut-off frequency is coupled to the

cut-off frequency of the LPF (Low-Pass Filter), and is

selectable in 4 steps: 1, 2, 4 and 10 MHz (see Table 2).

The HPF can be bypassed for SIG heads (see Table 8).

Low-pass filter

The second order low-pass filter is used to attenuate high

frequency noise above the signal bandwidth, mainly to

provide anti-aliasing filtering for the A/D converter in the

digital equalizer. The cut-off frequency of the LPF is

selectable in 4 steps: 1, 2, 4 and 10 MHz (see Table 2).

Sense current circuit

The sense current circuit is a programmable current

source, operating from the 12 V supply (VDD3). It can be

programmed to supply a current between 0 and 15 mA,

with 7-bit resolution. The current range can be doubled,

then ranging from 0 to 30 mA, by setting the SDB bit in the

control register (see Table 15). The sense current circuit

can be disabled by resetting the ENS bit (see Table 4).

This is the only circuit on the IC that uses the 12 V supply.

The output must be decoupled with a low impedance

capacitor (10 µF recommended) to reduce noise coupling

into the head.

For the current source circuit to operate correctly, the

voltage difference between VDD3 (pin 9) and ISENSE

(pin 8) must be at least 1.6 V.

1998 Mar 17

6

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