MSM82C37B-5GS Просмотр технического описания (PDF) - Oki Electric Industry
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MSM82C37B-5GS Datasheet PDF : 34 Pages
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¡ Semiconductor
MSM82C37B-5RS/GS/VJS
Slave Mode
Symbol
tAR
Item
Time from Address Valid or
CS Leading Edge to IOR Leading Edge
Min.
50
(Ta = –40 to +85°C, VCC = 4.5 to 5.5 V)
Max.
Unit
Comments
—
ns
—
Address Valid Set-up Time
tAW
to IOW Trailing Edge
CS Leading Edge Set-up Time
tCW
to IOW trailing edge
130
—
ns
—
130
—
ns
—
Data Valid Set-up Time
tDW
to IOW Trailing Edge
Address or CS Hold Time
tRA
to IOR Trailing Edge
130
—
ns
—
0
—
ns
—
Data Access Time
tRDE
to IOR Leading Edge
—
140
ns
—
Delay Time to Data Floating Status
tRDF
from IOR Trailing Edge
0
70
ns
—
tRSTD
Supply Power Leading Edge Set-up
time to RESET Trailing Edge
500
—
ns
—
tRSTS
Time to First Active IOR or IOW
from RESET Trailing Edge
2tCY
—
ns
—
tRSTW
tRW
RESET Pulse Width
IOR Pulse Width
300
—
ns
—
200
—
ns
—
Address Hold Time
tWA
to IOW Trailing Edge
20
—
ns
—
CS Trailing Edge Hold Time
tWC
to IOW Trailing Edge
20
—
ns
—
tWD
Data Hold Time to IOW Trailing Edge
30
—
ns
—
tWWS
IOW Pulse Width
160
—
ns
—
Notes: 1. Output load capacitance of 150 (pF).
2. IOW and MEMW pulse widths of tCY – 100 (ns) for normal writing, and 2tCY – 100
(ns) for extended writing. IOR and MEMR pulse widths of 2tCY – 50 (ns) for normal
timing, and tCY – 50 (ns) for compressed timing.
3. DREQ and DACK signal active level can be set to either low or high. In the timing
chart, the DREQ signal has been set to active-high, and the DACK signal to active-
low.
4. When the CPU executes continuous read or write in programming mode, the
interval during which the read or write pulse becomes active must be set to at least
400 ns.
5. EOP is an open drain output. The value given is obtained when a 2.2 kW pull-up
resistance is connected to VCC.
6. Rise time and fall time are less than 10 ns.
7. Waveform measurement points for both input and output signals are 2.2 V for HIGH
and 0.8 V for LOW, unless otherwise noted.
7/33
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