U636H04DC25 Просмотр технического описания (PDF) - Zentrum Mikroelektronik Dresden AG
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U636H04DC25 Datasheet PDF : 11 Pages
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U636H04
Preliminary
Device Operation
The U636H04 has two separate modes of operation:
SRAM mode and nonvolatile mode. In SRAM mode,
the memory operates as a standard fast static RAM. In
nonvolatile mode, data is transferred from SRAM to
EEPROM (the STORE operation) or from EEPROM to
SRAM (the RECALL operation). In this mode SRAM
functions are disabled.
STORE cycles may be initiated under user control via a
software sequence and are also automatically initiated
when the power supply voltage level of the chip falls
below VSWITCH. RECALL operations are automatically
initiated upon power up and may occur also when VCC
rises above VSWITCH after a low power condition.
SRAM READ
The U636H04 performs a READ cycle whenever E and
G are LOW and W are HIGH. The address specified on
pins A0 - A8 determines which of the 512 data bytes
will be accessed. When the READ is initiated by an
address transition, the outputs will be valid after a delay
of tcR. If the READ is initiated by E or G, the outputs will
be valid at ta(E) or at ta(G), whichever is later. The data
outputs will repeatedly respond to address changes
within the tcR access time without the need for transition
on any control input pins, and will remain valid until
another address change or until E or G is brought
HIGH or W is brought LOW.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
LOW. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until
either E or W goes HIGH at the end of the cycle. The
data on pins DQ0 - 7 will be written into the memory if it
is valid tsu(D) before the end of a W controlled WRITE or
tsu(D) before the end of an E controlled WRITE.
It is recommended that G is kept HIGH during the en-
tire WRITE cycle to avoid data bus contention on the
common I/O lines. If G is left LOW, internal circuitry will
turn off the output buffers tdis(W) after W goes LOW.
AUTOMATIC STORE
The U636H04 uses the intrinsic system capacitance to
perform an automatic STORE on power down. As long
as the system power supply take at least tPDSTORE to
decay from VSWITCH down to 3.6 V the U636H04 will
safely and automatically STORE the SRAM data in
EEPROM on power down.
In order to prevent unneeded STORE operations, auto-
matic STORE will be ignored unless at least one
WRITE operation has taken place since the most
recent STORE or RECALL cycle.
AUTOMATIC RECALL
During power up an automatic RECALL takes place.
After any low power condition (VCC < VSWITCH) an inter-
nal RECALL request may be latched. When VCC once
again exceeds the sense voltage of VSWITCH, a reque-
sted RECALL cycle will automatically be initiated and
will take tRESTORE to complete.
If the U636H04 is in a WRITE state at the end of a
power up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10 KΩ resistor should be
connected between W and system VCC.
HARDWARE PROTECTION
The U636H04 offers hardware protection against inad-
vertent STORE operation through VCC Sense. When
VCC < VSWITCH all software controlled STORE operati-
ons will be inhibited.
LOW AVERAGE ACTIVE POWER
The U636H04 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
The overall average current drawn by the part depends
on the following items:
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
6. the VCC level
10
December 12, 1997
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