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LTC1412IG

12-Bit, 3Msps, Sampling A/D Converter

Linear Technology 

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FUNCTIONAL BLOCK DIAGRA

LTC1412

AIN+

AIN–

VREF

2k

2.5V REF

CSAMPLE

CSAMPLE

ZEROING SWITCHES

AVDD

DVDD

REFCOMP

(4.06V)

AGND

DGND

REF AMP

12-BIT CAPACITIVE DAC

+

COMP

–

INTERNAL

CLOCK

SUCCESSIVE APPROXIMATION

REGISTER

CONTROL LOGIC

CONVST

CS

12

OUTPUT

LATCHES

•••

D11

D0

OVDD

OGND

BUSY

1412 BD

TEST CIRCUITS

Load Circuits for Access Timing

DBN

1k

5V

1k

DBN

CL

CL

A) HI-Z TO VOH AND VOL TO VOH

B) HI-Z TO VOL AND VOH TO VOL

1412 TC01

Load Circuits for Output Float Delay

5V

DBN

1k

DBN

100pF

1k

100pF

A) VOH TO HI-Z

B) VOL TO HI-Z

1412 TC02

APPLICATIONS INFORMATION

Conversion Details

The LTC1412 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit parallel output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. (Please refer to the Digital Interface

section for the data format.)

Conversion start is controlled by the CS and CONVST

inputs. At the start of the conversion the successive

approximation register (SAR) is reset. Once a conversion

cycle has begun it cannot be restarted.

During the conversion, the internal differential 12-bit

capacitive DAC output is sequenced by the SAR from the

most significant bit (MSB) to the least significant bit

(LSB). Referring to Figure 1, the AIN+ and AIN– inputs are

connected to the sample-and-hold capacitors (CSAMPLE)

during the acquire phase and the comparator offset is

nulled by the zeroing switches. In this acquire phase, a

minimum delay of 50ns will provide enough time for the

7

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