MAX5013AEPI Просмотр технического описания (PDF) - Maxim Integrated
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MAX5013AEPI Datasheet PDF : 8 Pages
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12-Bit, 100Msps TTL DAC
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5.0V, VEE = -5.2V, RSET = 7.5kΩ, Control Amp In = Ref Out, VOUT = 0V, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETERS
CONDITIONS
TEST
MAX5013A
LEVEL MIN TYP MAX
MAX5013B
MIN TYP MAX
UNITS
POWER-SUPPLY REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
IV
4.75
5.0
5.25
4.75
5.0
5.25
V
IV
-5.46 -5.2 -4.94 -5.46 -5.2 -4.94
Positive Supply Current (+5.0V) TA = +25°C
I
Full temperature
VI
8
14
16
8
14
mA
16
Negative Supply Current (-5.2V) TA = +25°C
I
Full temperature
VI
115
140
148
115
140
mA
148
Nominal Power Dissipation
V
640
640
mW
±5% of VEE and VCC,
Power-Supply Rejection Ratio external reference,
I
TA = +25°C
30
100
30
100
µA/V
VOLTAGE INPUT AND CONTROL
Reference Input Impedance
TA = +25°C
V
3
Reference Multiplying
Bandwidth
TA = +25°C
V
40
3
kΩ
40
MHz
Internal Reference Voltage
VI
-1.15 -1.20 -1.25 -1.15 -1.20 -1.25
V
Internal Reference Voltage Drift Full temperature
V
50
Amplifier Input Impedance
TA = +25°C
V
3
Amplifier Input Bandwidth
TA = +25°C
V
1
DIGITAL INPUTS
50
ppm/°C
3
MΩ
1
MHz
Logic 1 Voltage
Full temperature
VI
2.0
2.0
V
Logic 0 Voltage
Full temperature
VI
0.8
0.8
V
Logic 1 Current
Full temperature
VI
20
20
µA
Logic 0 Current
Full temperature
VI
600
600
µA
Input Capacitance
TA = +25°C
V
3
3
pF
Input Setup Time (tS)
TA = +25°C
Full temperature
IV
3
2
IV
3.5
3
2
3.5
ns
Input Hold Time (tH)
TA = +25°C
Full temperature
IV
0.5
0
IV
0.5
0.5
0
0.5
ns
Latch Pulse Width (tPWL, tPWH) TA = +25°C
IV
5.0
4.0
5.0
4.0
ns
Note 1: Gain is measured as a ratio of the full-scale current to ISET. The ratio is nominally 128.
Note 2: Measured as voltage at mid-scale transition to ±0.024%; RL = 50Ω.
Note 3: Measured from the rising edge of Latch Enable to where the output signal has left a 1LSB error band.
Note 4: Glitch is measured as the largest single transient.
Note 5:
Calculated using
I FS
=
128
x
Control Amp
RSET
In
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