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MK2703I

PLL Audio Clock Synthesizer

Integrated Circuit Systems 

I CR O C LOC K

MK2703

PLL Audio Clock Synthesizer

Electrical Specifications

Parameter

Conditions

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

Inputs and Clock Outputs

Referenced to GND

Ambient Operating Temperature

MK2703S

MK2703SI

Soldering Temperature

Max of 10 seconds

Storage temperature

DC CHARACTERISTICS (VDD = 3.3 V unless noted)

Operating Voltage, VDD

Input High Voltage, VIH, X1 pin only

Input Low Voltage, VIL, X1 pin only

Input High Voltage, VIH

Input Low Voltage, VIL

Output High Voltage, VOH

IOH=-12mA

Output Low Voltage, VOL

IOL=12mA

Output High Voltage, VOH, CMOS level

IOH=-4mA

Operating Supply Current, IDD

No Load

Short Circuit Current

Each output

Input Capacitance

S1, S0

Frequency synthesis error

All clocks

AC CHARACTERISTICS (VDD = 3.3 V unless noted)

Input Crystal Frequency

Input Crystal Accuracy

Output Clock Rise Time

0.8 to 2.0V

Output Clock Fall Time

2.0 to 0.8V

Output Clock Duty Cycle

At VDD/2

Maximum Absolute Jitter, short term

Minimum Typical Maximum Units

7

V

-0.5

VDD+0.5 V

0

70

°C

-40

85

°C

260

°C

-65

150

°C

3.13

5.50

V

(VDD/2)+1 VDD/2

V

VDD/2 (VDD/2)-1 V

2

V

0.8

V

2.4

V

0.4

V

VDD-0.4

V

25

mA

±50

mA

5

pF

0

ppm

27.00

MHz

±30

ppm

1.5

ns

1.5

ns

40

60

%

±190

ps

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

External Components

The MK2703 requires a minimum number of external components for proper operation. For a crystal input,

one load capacitor should be connected from each of the X1 and X2 pins to ground. The value (in pF) of

each crystal load capacitor should equal (CL-16)•2, where CL is the crystal’s load (correlation) capacitance

in pF. The input crystal must be connected as close to the chip as possible. The input crystal should be a

parallel resonant, fundamental, AT cut 27 MHz. For a clock input, connect to X1 and leave X2

unconnected. Decoupling capacitors of 0.01µF should be connected between VDD and GND on pins 2

and 3, as close to the MK2703 as possible. A series termination resistor of 33 Ω may be used for the clock

output.

MDS 2703 C

3

Revision 062700

Printed 11/16/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com

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