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PI74ALVCHR16269V

12-Bit to 24-Bit Registered Bus Exchanger With 3-STATE Outputs

Pericom Semiconductor 

PI74ALVCHR16269

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12-Bit to 24-Bit Registered Bus Exchanger

With 3-STATE Outputs

Product Features

• PI74ALVCHR16269 is designed for low voltage operation

• VCC = 2.3V to 3.6V

• Hysteresis on all inputs

• Typical VOLP (Output Ground Bounce)

< 0.8V at VCC = 3.3V, TA = 25°C

• Typical VOHV (Output VOH Undershoot)

< 2.0V at VCC = 3.3V, TA = 25°C

• All output ports have equivalent 26Ω series resistors,

no external resistors are required

• Bus Hold retains last active bus state during 3-STATE,

eliminating the need for external pullup resistors

• Industrial operation at –40°C to +85°C

• Packages available:

– 56-pin 240 mil wide plastic TSSOP (A)

– 56-pin 300 mil wide plastic SSOP (V)

Product Description

Pericom Semiconductor’s PI74ALVCH series of logic circuits are

produced in the Company’s advanced 0.5 micron CMOS technology,

achieving industry leading speed.

The PI7ALVCHR16269 is used in applications in which two separate

ports must be multiplexed onto, or demultiplexed from, a single port.

It is particularly suitable as an interface between synchronous DRAM’s

and high-speed microprocessors.

Data is stored on the internal B-port registers on the low-to-high

transition of the clock (CLK) input when the appropriate clock-enable

(CLKENA) inputs are low. Proper control of these inputs allows two

sequential 12-bit words to be presented as a 24-bit word on the B-port.

For data transfer in the B-to-A direction, a single storage register is

provided. The select (SEL) line selects 1B or 2B data for the A outputs.

The register on the A output permits the fastest possible data transfer,

thus extending the period during which the data is valid on the bus. The

control terminals are registered so that all transactions are synchronous

with CLK. Data flow is controlled by the active-low output enables

(OEA, OEB1, and OEB2).

Logic Block Diagram

To ensure the high-impedance state during power up or power

down, a clock pulse should be applied as soon as possible and OE

should be tied to VCC through a pullup resistor; the minimum value

of the resistor is determined by the current-sinking capability of the

driver. Due to OE being routed through a register, the active state

of the outputs cannot be determined prior to the arrival of the first

clock pulse.

Active bus-hold circuitry is provided to hold unused or floating

data inputs at a valid logic level.

All outputs are designed to sink up to 12mA and include 26Ω

resistors to reduce overshoot and undershoot.

1

PS8372 01/28/99

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