V300PSC Просмотр технического описания (PDF) - QuickLogic Corporation

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V300PSC

PCI Bus Target Interface

QuickLogic Corporation 

V300PSC

Table 16: PCI Bus Timing Parameters for Vcc = 5 Volts +/- 5%

# Symbol

Description

1

TC PCLK period

2

TSU Synchronous input setup to PCLK

3

TH Synchronous input hold from PCLK

4 TCOV PCLK to output valid delay

5 TCZO PCLK to output driving delay

6 TCOZ PCLK to high impedance delay

7 TRST Reset period

Notes Min Max Units

30

ns

1

7

ns

0

ns

2

3

11 ns

4

11 ns

5

18 ns

16·TC

4.3 Serial EEPROM Port TImings

The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms

generated are shown in Figure 6.

Figure 6: Serial EEPROM Waveforms and Timings

START CONDITION

512 PCI BUS

CLOCKS

STOP CONDITION

SCL

SDA

256 PCI BUS

CLOCKS

256 PCI BUS

CLOCKS

Copyright © 1997, V3 Semiconductor Corp.

V300PSC Data Sheet Rev 1.1

17

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