OR3LP26B Просмотр технического описания (PDF) - Agere -> LSI Corporation
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OR3LP26B
Agere -> LSI Corporation
OR3LP26B Datasheet PDF : 184 Pages
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ORCA OR3LP26B FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
OR3LP26B Overview
Device Layout
The OR3LP26B FPSC provides a PCI local bus core
(with FIFOs) combined with FPGA logic. The device is
based on a 2.5 V OR3L125B FPGA. The OR3L125B
has a 28 x 28 array of programmable logic cells (PLCs).
For the OR3LP26B, the bottom ten rows of PLCs in the
array were replaced with the embedded PCI bus core.
Table 3 shows a schematic view of the OR3LP26B. The
upper portion of the device is an 18 x 28 array of PLCs
surrounded on the left, top, and right by programmable
input/output cells (PICs). At the bottom of the PLC
array are the core interface cells (CICs) connecting to
the embedded core region. The embedded core region
contains the PCI bus functionality of the device. It is
surrounded on the left, bottom, and right by PCI bus
dedicated I/Os as well as power and special function
FPGA pins. Also shown are the interquad routing
blocks (hIQ, vIQ) present in the Series 3 FPGA
devices. System-level functions (located in the corners
of the PLC array), routing resources, and configuration
RAM are not shown in Figure 1.
Table 2. PCI Local Bus Data Rates
Clock
Frequency
(MHz)
33
33
66
66
Data Path
Width (bits)
32
64
32
64
Peak Data Rate
(Mbytes)
132
264
264
528
The PCI bus is electrically specified so that no glue
logic is required to interface to the bus—PCI devices
interface directly to the PCI bus. Other features include
registers for device and subsystem identification and
autoconfiguration, support for 64-bit addressing, and
multi-Master capability that allows any PCI bus Master
access to any PCI bus Target.
PCI Local Bus
PCI local bus, or simply, PCI bus, has become an
industry-standard interface protocol for use in applica-
tions ranging from desktop PC busing to high-band-
width backplanes in networking and communications
equipment. The PCI bus specification* provides for
both 5 V and 3.3 V signaling environments. The inter-
face clock speed is specified in the range from dc to
66 MHz with detailed specifications at 33 MHz and
66 MHz as well as recommendations for 50 MHz oper-
ation. Data paths are defined as either 32-bit or 64-bit.
These data path and frequency combinations allow for
the peak data transfer rates described in Table 2.
* PCI Local Bus Specification Rev. 2.2, PCI SIG, December 18,
1998.
10
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