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OR3TP12

ORCA® OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Agere -> LSI Corporation 

Data Sheet

March 2000

ORCA OR3TP12 FPSC

Embedded Master/Target PCI Interface

PCI Bus Core Highlights (continued)

s Operates at PCI bus speeds up to 66 MHz.

s Comprises two independent controllers for Master

and Target.

s Meets/exceeds all requirements for PICMG *Hot

Swap Friendly silicon, Full Hot Swap model, per the

CompactPCI* Hot Swap Specification, PICMG 2.1

R1.0.

s PCI SIG Hot-Plug (R1.0) compliant.

s Four internal FIFOs individually buffer both directions

of both the Master and Target interfaces:

— Both Master FIFOs are 64 bits wide by 32 bits

deep.

— Both Target FIFOs are 64 bits wide by 16 bits

deep.

s Capable of no-wait-state, full-burst PCI transfers in

either direction, on either the Master or Target inter-

face. Dual 32-bit data paths extend into the FPGA

logic, permitting full-bandwidth, simultaneous bidirec-

tional data transfers of up to 264 Mbytes/s to be sus-

tained indefinitely.

s Can be configured to provide either two 32-bit buses

(one in each direction) to be multiplexed between

Master and Target, or four independent 16-bit buses.

s Provides many hardware options in the PCI bus core

that are set during FPGA logic configuration.

s Operates within the requirements of the PCI 5 V and

3.3 V signaling environments, allowing the same

device to be used in 5 V or 3.3 V PCI systems.

s FPGA is reconfigurable via the PCI interface configu-

ration space (as well as conventionally), allowing the

FPGA to be field-updated to meet late-breaking

requirements of emerging protocols.

s Master:

— Generates all defined command codes except

interrupt acknowledge and special cycle.

— Capable of acting as the system's configuration

agent by booting up with the Master logic enabled.

— Provides multiple options to increase PCI bus

bandwidth.

s Target:

— Responds legally to most command codes: inter-

rupt acknowledge, special cycle, and reserved

commands ignored; memory read multiple and

line handled as memory read; memory write and

invalidate handled as memory write.

— Implements Target abort, disconnect, retry, and

wait cycles.

— Handles delayed transactions.

— Handles fast back-to-back transactions.

— Supports programmable latency timer control.

— Method of handling wait-states is programmable

to allow tailoring to different Target data access

latencies.

— Decodes at medium speed.

s Supports dual-address cycles (both as Master and

Target).

s Supports all six base address registers (BARs), as

either memory (32-bit or 64-bit) or I/O. Any legal

page size can be independently specified for each

BAR during FPGA configuration.

s Provides versatile clocking capabilities with FPGA

clocks sourced from PCI bus clock or elsewhere.

FIFO interface buffers asynchronous clock domains

between the PCI interface and FPGA-based logic.

s PCI interface timing: meets or exceeds 33 MHz,

50 MHz, and 66 MHz PCI requirements.

Parameter

Device clock = > out

Device setup time

Board prop. delay

Board clock skew

Total budget

33 MHz 50 MHz 66 MHz

11.0 ns 7.5 ns 6.0 ns

7.0 ns 4.5 ns 3.0 ns

10.0 ns 6.5 ns 5.0 ns

2.0 ns 1.5 ns 1.0 ns

30.0 ns 20.0 ns 15.0 ns

s Standard 256-byte PCI configuration space:

— Class code, revision ID.

— Latency timer.

— Cache line size.

— Subsystem ID.

— Subsystem vendor ID.

— Maximum latency, minimum grant.

— Interrupt line.

— Hot plug/hot swap capability.

* CompactPCI and PICMG are registered trademarks of the PCI

Industrial Computer Manufacturers Group.

Lucent Technologies Inc.

5

Lucent Technologies Inc.

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