SAA7110 Просмотр технического описания (PDF) - Philips Electronics

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SAA7110

One Chip Front-end 1 (OCF1)

Philips Electronics 

Philips Semiconductors

One Chip Front-end 1 (OCF1)

Product specification

SAA7110; SAA7110A

9.4 Luminance processing (see Fig.7)

The 8-bit luminance signal, a digital CVBS format or a

luminance format (S-VHS, HI8), is fed through a

switchable prefilter. High frequency components are

emphasized to compensate for loss. The following

chrominance trap filter (fc = 4.43 or 3.58 MHz centre

frequency selectable) eliminates most of the colour carrier

signal, therefore, it must be bypassed for S-Video (S-VHS,

HI8) signals.

The high frequency components of the luminance signal

can be peaked (control for sharpness improvement via

I2C-bus) in two bandpass filters with selectable transfer

characteristics.

A coring circuit with selectable characteristics improves

the signal once more. This signal is then added to the

original (unpeaked) signal. A switchable amplifier achieves

common DC amplification, because the DC gains are

different in both chrominance trap modes.

The improved luminance signal is fed via the variable

delay to the BCS control and the output interface.

9.5 YUV-bus (digital outputs)

The 16-bit YUV-bus transfers digital data from the output

interfaces to a feature box, or a field memory, a digital

colour space converter (SAA 7192 DCSC) or a video

enhancement and digital-to-analog processor (SAA7165

VEDA2). The outputs are controlled by an output enable

chain (FEIN on pin 63).

The YUV data rate equals LLC2. Timing is achieved by

marking each second positive rising edge of the clock LLC

in conjunction with CREF (clock reference).

The output signals Y7 to Y0 are the bits of the digital

luminance signal. The output signals UV7 to UV0 are the

bits of multiplexed colour difference signals (B−Y) and

(R−Y). The frame in the format tables is the time, required

to transfer a full set of samples. In the event of 4 : 2 : 2

format two luminance samples are transmitted in

comparison to one U and one V sample within the frame.

The time frames are controlled by the HREF signal.

Fast enable is achieved by setting input FEIN to LOW. The

signal is used to control fast switching on the digital

YUV-bus. HIGH on this pin forces the Y and UV outputs to

a high-impedance state.

The synchronization pulses are sliced and fed to the phase

detectors where they are compared with the sub-divided

clock frequency. The resulting output signal is applied to

the loop filter to accumulate all phase deviations.

Adjustable output signals HCL and HSY are generated in

accordance with analog front end requirements. The

output signals HS, VS, and PLIN are locked to the timing

reference, guaranteed between the input signal and the

HREF signal, as further improvements to the circuit may

change the total processing delay. It is therefore not

recommended to use them for applications which require

absolute timing accuracy to the input signals. The loop

filter signal drives an oscillator to generate the line

frequency control signal LFCO.

9.7 Clock generation circuit

The internal CGC generates all clock signals required for

the one chip front-end. The output signal LFCO is a

digital-to-analog converted signal provided by the

horizontal PLL. It is the multiple of the line frequency

(7.38 MHz = 472 × fh in 50 Hz systems and

6.14 MHz = 360 × fh in 60 Hz systems). Internally the

LFCO signal is multiplied by a factor of 2 or 4 in the PLL

circuit (including phase detector, loop filtering, VCO and

frequency divider) to obtain the LLC and LLC2 output clock

signals. The rectangular output clocks have a 50% duty

factor.

It is also possible to operate the OCF1 with an external

CGC (SAA7197) providing the signals LLC and CREF.

The selection of the internal/external CGC will be

controlled by the CGCE input signal.

9.8 Power-on reset

Power-on reset is activated at power-on (using only

internal CGC), when the supply voltage decreases below

3.5 V. The indicator output RESET is LOW for a time. The

RESET signal can be applied to reset other circuits of the

digital TV system.

9.9 RTCO output

The real time control and status output signal contains

serial information about actual system clock, subcarrier

frequency and PAL/SECAM sequence. The signal can be

used for various applications in external circuits, for

example, in a digital encoder to achieve clean encoding.

9.6 Synchronization (see Fig.7)

The pre-filtered luminance signal is fed to the

synchronization stage. It's bandwidth is reduced to 1 MHz

in a low-pass filter.

1995 Oct 18

11

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