IN74ACT573DW Просмотр технического описания (PDF) - Integral Corp.

Номер в каталоге

Компоненты Описание

Список матч

IN74ACT573DW

OCTAL 3-STATE NONINVERTING TRANSPARENT LATCH High-Performance Silicon-Gate CMOS

Integral Corp. 

IN74ACT573

AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25 °C

-40°C to

Unit

85°C

Min Max Min Max

tPLH Propagation Delay, Input D to Q (Figure 1) 2.5 10.5 2.0 12

ns

tPHL Propagation Delay, Input D to Q (Figure 1) 2.5 10.5 2.0 12

ns

tPLH Propagation Delay,Latch Enableto Q 3.0 10.5 2.5 12

ns

(Figure 2)

tPHL Propagation Delay,Latch Enableto Q 2.5 9.5 2.0 10.5 ns

(Figure 2)

tPZH Propagation Delay, Output Enable to Q 2.0 10 1.5 11

ns

(Figure 3)

tPZL Propagation Delay, Output Enable to Q 1.5 9.5 1.5 10.5 ns

(Figure 3)

tPHZ Propagation Delay, Output Enable to Q 2.5 11 1.5 12.5 ns

(Figure 3)

tPLZ Propagation Delay, Output Enable to Q 1.5 8.5 1.0 9.5

ns

(Figure 3)

CIN Maximum Input Capacitance

5.0

5.0

pF

CPD Power Dissipation Capacitance

Typical @25°C,VCC=5.0 V

25

pF

TIMING REQUIREMENTS (VCC=5.0 V ± 10%, CL=50pF, Input tr=tf=3.0 ns)

Guaranteed Limit

Symbol

Parameter

25°C

-40°C to 85°C Unit

tSU Minimum Setup Time, Input D to Latch

3.0

Enable (Figure 4)

3.5

ns

th Minimum Hold Time, Latch Enable to

0

Input D (Figure 4)

0

ns

tw Minimum Pulse Width, Latch Enable

3.5

(Figure 2)

4.0

ns

4

Share Link: