MC74HC540ADT Просмотр технического описания (PDF) - ON Semiconductor
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MC74HC540ADT Datasheet PDF : 8 Pages
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MC74HC540A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V –55 to 25°C ≤85°C ≤125°C Unit
VIH
Minimum High–Level Input Voltage Vout = 0.1 V
|Iout| ≤ 20 mA
VIL
Maximum Low–Level Input Voltage Vout = VCC – 0.1 V
|Iout| ≤ 20 mA
2.0
1.50
1.50
1.50
V
3.0
2.10
2.10 2.10
4.5
3.15
3.15 3.15
6.0
4.20
4.20 4.20
2.0
0.50
0.50
0.50
V
3.0
0.90
0.90 0.90
4.5
1.35
1.35 1.35
6.0
1.80
1.80 1.80
VOH
Minimum High–Level Output Voltage Vin = VIL
|Iout| ≤ 20 mA
2.0
1.9
4.5
4.4
6.0
5.9
1.9
1.9
V
4.4
4.4
5.9
5.9
Vin = VIL
|Iout| ≤ 3.6 mA 3.0
2.48
2.34 2.20
|Iout| ≤ 6.0 mA 4.5
3.98
3.84 3.70
|Iout| ≤ 7.8 mA 6.0
5.48
5.34 5.20
VOL
Maximum Low–Level Output Voltage Vin = VIH
|Iout| ≤ 20 mA
2.0
0.1
4.5
0.1
6.0
0.1
0.1
0.1
V
0.1
0.1
0.1
0.1
Vin = VIH
|Iout| ≤ 3.6 mA 3.0
0.26
0.33 0.40
|Iout| ≤ 6.0 mA 4.5
0.26
0.33 0.40
|Iout| ≤ 7.8 mA 6.0
0.26
0.33 0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
±0.1
±1.0
±1.0 mA
IOZ
Maximum Three–State Leakage
Output in High Impedance State
6.0
±0.5
±5.0 ±10.0 mA
Current
Vin = VIL or VIH
Vout = VCC or GND
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
4
40
160 mA
8. Information on typical parametric values can be found in the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
Guaranteed Limit
VCC
V –55 to 25°C ≤85°C ≤125°C Unit
tPLH, Maximum Propagation Delay, Input A to Output Y
tPHL (Figures 3 and 5)
2.0
80
3.0
30
4.5
18
6.0
15
100
120
ns
40
55
23
28
20
25
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
110
3.0
45
4.5
25
6.0
21
140
165
ns
60
75
31
38
26
31
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
2.0
110
3.0
45
4.5
25
6.0
21
140
165
ns
60
75
31
38
26
31
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
2.0
60
3.0
22
4.5
12
6.0
10
75
90
ns
28
34
15
18
13
15
Cin
Maximum Input Capacitance
10
10
10
pF
Cout Maximum Three–State Output Capacitance (Output in High Impedance State)
15
15
15
pF
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High–Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Per Buffer) (Note 10.)
35
pF
10. Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
http://onsemi.com
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