SAM4CP16B Datasheet PDF - Atmel Corporation

Description
The SAM4CP series belongs to Atmel® │SMART energy portfolio. It is based on SAM4C, a high performance 32-bit, dual core ARM® Cortex®-M4 RISC processor embedding a PRIME PLC [Power Line Communication] modem. The cores are able to operate at a maximum speed of 120 MHz, featuring 1 Mbyte of embedded Flash, 128 kBytes of SRAM and on-chip cache for each core.
SAM4CP unique dual ARM Cortex-M4 architecture supports implementation of signal processing, application and communications firmware in independent partitions. SAM4CP16B system-on-chip includes a PRIME modem, being PRIME [PoweR line Intelligent Metering Evolution] an open standard technology used for Smart Grid applications, mainly Smart Metering. Atmel PRIME modem implementation includes enhanced PHY layer features such as additional robust modes and frequency band extension.

Features
● Application/Master Core (CM4P0)
   ● ARM Cortex-M4 running at up to 120 MHz(1)
   ● Memory Protection Unit (MPU)
   ● DSP Instruction
   ● Thumb®-2 instruction set
   ● Instruction and Data Cache Controller with 2 Kbytes Cache Memory
   ● Memories
      ● 1024 Kbytes of Embedded Flash for Program Code (I-Code bus) and Program Data
         (D-Code bus)
         with Built-in ECC (2-bit error detection and 1-bit correction per 128 bits)
      ● 128 Kbytes of Embedded SRAM (SRAM0) for Program Data (System bus)
      ● 8 Kbytes of ROM with embedded boot loader routines (UART) and In-Application
         Programming (IAP) routines
● Co-processor (CM4P1), provides ability to separate application, communication or metrology
   functions
   ● ARM Cortex-M4F running at up to 120 MHz
   ● IEEE® 754 Compliant, Single precision Floating-Point Unit (FPU)
   ● DSP Instruction
   ● Thumb-2 instruction set
   ● Instruction and Data Cache Controller with 2 Kbytes Cache Memory
   ● Memories
      ● 16 Kbytes of Embedded SRAM (SRAM1) for Program Code (I-Code bus) and
         Program Data (D-Code bus and System bus)
      ● 8 Kbytes of Embedded SRAM (SRAM2) for Program Data (System bus)
● Symmetrical/Asynchronous Dual Core Architecture
   ● Interrupt-based Interprocessor Communication
   ● Asynchronous Clocking
   ● One Interrupt Controller (NVIC) for each core
   ● Each Peripheral IRQ routed to each NVIC Input
● Cryptography
   ● High-performance AES 128 to 256 with various modes
      (GCM, CBC, ECB, CFB, CBC-MAC, CTR)
   ● TRNG (up to 38 Mbit/s stream, with tested Diehard and FIPS)
   ● Classical Public Key Crypto accelerator and associated ROM library
      for RSA, ECC, DSA, ECDSA
   ● Integrity Check Module (ICM) based on Secure Hash Algorithm
      (SHA1, SHA224, SHA256), DMA assisted
● Safety
   ● 4 Physical Anti-tamper Detection I/O with Time Stamping and Immediate Clear
      of General Backup Registers
   ● Security bit for Device Protection from JTAG accesses
● Shared System Controller
   ● Power Supply
      ● Embedded Core and LCD Voltage Regulator for single supply operation
      ● Power-on-Reset (POR), Brownout Detector (BOD) and Watchdog for safe operation
      ● Low Power Sleep and Backup modes
   ● Clock
      ● 3 to 20 MHz Quartz or ceramic resonator oscillators with Clock Failure Detection
      ● Optional low-power 32.768 kHz crystal oscillator for RTC
      ● High precision 4/8/12 MHz factory trimmed internal RC oscillator
         with on-the-fly trimming capability
      ● One High Frequency PLL up to 240 MHz, One 8 MHz PLL with internal 32 kHz input,
         as source for High Frequency PLL
      ● Low power Slow Clock Internal RC oscillator as permanent clock (Continue ...)