Address
CS
CS
R/W
Data In
tAS
tRCS
Read Cycle Timing
tcyc(R)
tacc
tDDR
tAH
tRH
tDHA
tDHR
tH
Data Valid
Note 1. Voltage levels shown are VL ≤ 0.4V, VH ≥ 2.4V, unless otherwise specified.
Note 2. Measurement pointas shown are 0.8V and 2.0V, unless otherwise specified.
Note 3. CS and CS have same timing.
Write Cycle Timing
= Don’t Care
Address
CS
CS
R/W
Data In
tAS
tWCS
tcyc(W)
tCS
tAH
tWH
tDSW
tH
Data in Stable
Note 1. Voltage levels shown are VL ≤ 0.4V, VH ≥ 2.4V, unless otherwise specified.
Note 2. Measurement pointas shown are 0.8V and 2.0V, unless otherwise specified.
Note 3. CS and CS have same timing.
= Don’t Care