SL74HC165D Просмотр технического описания (PDF) - System Logic Semiconductor

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SL74HC165D

8-Bit Serial or Parallel-Input/Serial-Output Shift Register High-Performance Silicon-Gate CMOS

System Logic Semiconductor 

SL74HC165

AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)

Symbol

Parameter

fmax Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 8)

tPLH, tPHL Maximum Propagation Delay, Clock (or Clock

Inhibit) to QH or QH (Figures 1 and 8)

tPLH, tPHL

tPLH, tPHL

Maximum Propagation Delay , SerialShift./.Parallel

Load to QH or QH

(Figures 2 and 8)

Maximum Propagation Delay, Input H to QH or QH

(Figures 3 and 8)

tTLH, tTHL Maximum Output Transition Time, Any Output

(Figures 1 and 8)

CIN

Maximum Input Capacitance

VCC

Guaranteed Limit

V 25 °C to ≤85°C ≤125°C

-55°C

2.0 6.0

4.8

4.0

4.5 30

24

20

6.0 35

28

24

2.0 150

190

225

4.5 30

38

45

6.0 26

33

38

2.0 175

220

265

4.5 35

44

53

6.0 30

37

45

2.0 150

190

225

4.5 30

38

45

6.0 26

33

38

2.0 75

95

110

4.5 15

19

22

6.0 13

16

19

-

10

10

10

Unit

MHz

ns

ns

ns

ns

pF

Power Dissipation Capacitance (Per Package)

CPD Used to determine the no-load dynamic power

consumption:

PD=CPDVCC2f+ICCVCC

Typical @25°C,VCC=5.0 V

85

pF

SLS

System Logic

Semiconductor

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