ICM107B Mega pixel CMOS sensor
Data sheet Version 0.5, January 2002
5.3 Pixel Clock Duty Cycle
In different frame rate mode (controlled by PART_CONTROL [6:4]), the duty cycle (high time / clock
period) of the PCLK signal is described in the following table:
Frame Rate
30
15
10
5
4
3
2
1
Duty Cycle
50.0%
50.0%
50.0%
50.0%
53.3%
50.0%
50.0%
50.0%
©2000, 2001,2002 IC Media Corporation & IC Media Technology Corp
web site: http://www.ic-media.com/
web site: http://www.ic-media.com.tw/
page 18
10/29/2002
Confidential