EDS1232AATA-MI
Read command (/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been met. This command sets the burst start address
given by the column address.
CLK
CKE H
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
E A10
Add
Col.
Column Address and and Read Command
OCBR (auto) refresh command (/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle
(precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or
L activate command), the Synchronous DRAM cannot accept any other command
CLK
CKE H
/CS
/RAS
P/CAS
/WE
BA0, BA1
(Bank select)
rA10
Add
oduct CBR (auto) Refresh Command
Data Sheet E0340E30 (Ver. 3.0)
13